The present invention relates to semiconductor integrated circuits including a clock generation circuit, and more particularly to semiconductor integrated circuits in which a PLL (phase-locked loop) circuit is provided.
Computing systems, such as microprocessors or microcontrollers, are provided with PLL circuits functioning as a clock multiplier circuit in order to realize the function of multiplying an external frequency at a portion of the central processing unit to perform high-speed operations. Furthermore, in recent microprocessors, it is desirable to be able to maintain the clock phase between an external bus and within the semiconductor integrated circuit with high precision.
In conventional methods, the time that it takes until the PLL circuit stabilizes after the power has been turned on is counted with a timer, the clock supply from the PLL circuit to the central processing unit is halted for a certain amount of time, and the multiplied clock supply is started as soon as the timer overflows.
Now, in the phase comparator of the PLL circuit it is desirable that there is a linear relation between the phase difference of the two signals entered into it and the voltage that is output. However in practice, there are cases in which it is not possible to detect tiny phase differences, so that there may be a dead zone of phase differences, and there may be discontinuities when the sensitivity is too high.
It is known that the length of the delay time in the reset circuit has a large influence on the input/output characteristics of the phase comparator. In other words, in order to improve the input/output characteristics of the phase comparator, it is necessary to adjust the delay time in the reset circuit to an appropriate value. However, in the phase comparator according to a first piece of conventional technology, the delay time becomes shorter than the appropriate value because the reset circuit is made of one 4-input NAND circuit, and the input/output characteristics exhibit a dead zone (U.S. Pat. No. 3,610,954).
Several improvements have been suggested in order to adjust the delay time of the reset circuit to an appropriate value. In a second piece of conventional technology, the output of the reset signal is delayed by making the channel width of a transistor constituting the 4-input NAND circuit narrower (JP S63-119318A). Furthermore, in a third piece of conventional technology, a plurality of capacitors are used as a means for delaying the output of the reset signal (U.S. Pat. No. 4,378,509).
As described above, in the phase comparator according to the first conventional technology, the reset circuit is constituted by one 4-input NAND circuit, so that the delay time becomes shorter than the appropriate value and there is a dead zone in the input/output characteristics. In the case of the second conventional technology, a worsening of the yield due to variations in the channel width or the like has become unavoidable with the sub-micron gate widths of recent transistors. And with the third conventional technology, the capacitors lead to an increase of the chip surface area.
Charge pump circuits also have an aspect that worsens their input/output characteristics. When using a current-type charge pump circuit, it occurs that the output voltage of the phase comparator changes even though there is no phase difference between the two input signals. This means that even though clocks of the same phase are input, the phase difference is detected erroneously and a highly accurate PLL circuit cannot be realized.
Furthermore, clock drivers are designed such that they can supply a clock synchronized with zero skew to the function blocks, but due to temperature dependencies, process variations and the like, there are skew variations among chips.
Also, inside the function blocks, circuits that use two phases of clocks with clock synchronization, such as dynamic circuits or memories, are designed such that they can operate stably with some delay so as to avoid signal racing, but due to process variations, the margin between the two phases of the clocks may disappear, resulting in faulty operation.
Furthermore, there are function blocks that include the function of interrupting a series of operations when processing has become unnecessary during that series of operations, in order to reduce energy consumption, but depending on the operation frequency and process variations, the operation may not be halted completely, resulting in faulty operation.
Moreover, providing a tuning circuit in order to solve these problems is a waste of time, because the start of the operation of the tuning circuit needs to wait until the PLL circuit has stabilized.